Word alignment problems with memory addressing

Category: C/C++ -> C++ Author: chenchen1818 Date: 2009-05-01 09:28:03
 
chenchen1818
2009-05-01 09:28:03
Look << Windows Game Programming Gurus >> just turned a few pages.
book said that as an example does not consider the word aligned memory addressing will appear when the big problem.
I want to know there will be a big problem?
addition to the previously authors say, because of cache and other relevant internal memory addressing become less regular, smaller data may cause slowdowns.
join0807
2009-05-01 09:47:14
do not know can not be that good, try:
if the memory according to the following arrangement:
....
00000003 (odd bits) 00000004 (even bit)
00000001 (odd bits) 00000002 (even bits)
(last digit indicates the byte sequence does not mean values)
assumption is 16-bit machine, once read two byte .. ie either a read 1 and 2 (if a data is stored in 1 and 2, as long as you can get read once), or one read 3 and 4 .. If our data in computer memory are closely spaced (unrealized word aligned), for example, are stored in a data sequence 2 and sequence 3 ... then we must continuously read twice the memory, first get the sequence 2 and then get the sequence 3, then adjust the parity can get such a data .... So, if we are to achieve a word-aligned, such that the sequence 3 and sequence data into four, then you can get the upgrade operation, but it will waste space (after all, did not use the sequence 2 ) ...
ydc666888
2009-05-01 10:02:31
Modern computer memory space is divided by byte, in theory seem to access any type of variable can be started from any address, but the reality is that access to specific types of variables in often when accessing a specific memory address (like a store one byte is not possible to start the first three, more than one byte of the first two ends) which requires various types of data according to certain rules in space arrangement instead of a bit sequence by one bit of the discharge, which is aligned alignment ...
role and causes: each hardware platform for storage space there is a great deal different. Some platforms for certain types of data can only be accessed from a specific address to start. For example, some CPU architecture to access a variable that is not aligned when an error occurs, then in this framework program must ensure that the byte alignment. Other platforms may not be the case, but the most common is if you do not follow suit their platform requirements for data storage alignment will cause losses on the access efficiency. For example, some platforms are each read address from the beginning even if an int type (assumed to be 32-bit systems) if stored in an even address the place to start, then a read cycle can read this 32bit, and if stored in an odd address place to start, you need two read cycles, and read out the results of two nibbles for patchwork to get the 32bit data. Obviously a lot of reading efficiency decreased.
jiedie57
2009-05-01 10:19:08
consider the word alignment, memory addressing will greatly accelerate the speed,
but it will cause some wasted space! ! !

willyaoyao
2009-05-01 10:35:41


here you can come to a halt, and then down it should be related to the hardware design aspects of the
a224182
2009-05-01 10:41:33
Thank a floor
other friends have other ideas?
illisillis
2009-05-01 11:00:37
to 3 floor
and if stored in an odd address the place to start, you need two read cycles, and read out the results of two nibbles for patchwork to get the 32bit data.

This sentence can specifically explain this?
penghuafang
2009-05-01 11:05:01
really are interested to see SCM principles like the book.